• 专利附录
  • 专利说明
  • 权利要求
  • 类似技术
  • 同族专利
  • 引用文献
  • 法律状态
  • 优先权
    • 专利摘要:
    A circuit for providing an output voltage for a DRAM word line which can be used to drive memory word lines which can be as high as 2Vdd. Transistors in a boosting circuit are fully switched, eliminating the reduction of the boosting voltage by Vtn as in the prior art. The boosting capacitors are charged by Vdd, thus eliminating drift tracking problems associated with clock boosting sources and Vdd. A regulator detects conduction current of a replica of a memory cell access transistor, shutting off the boosting circuit clock oscillator when the correct voltage to operate the access transistor has been reached.
    公开号:US20010009518A1
    申请号:US09/819,488
    申请日:2001-03-28
    公开日:2001-07-26
    发明作者:Richard Foss；Peter Gillingham；Robert Harland；Valerie Lines
    申请人:Mosaid Technologies Inc；
    IPC主号:G11C5-145
    专利说明:
    [0001] This invention relates to dynamic random access memories (DRAMs) and in particular to a boosted word line power supply charge pump and regulator for establishing word line voltage. [0001] BACKGROUND TO THE INVENTION
    [0002] High density commercial DRAMS typically use capacitive pump voltage boosting circuits for providing sufficiently high voltage to drive DRAM word lines. Regulation of the voltage has been poor, and danger exists of generating voltages above the limits imposed by reliability requirements of the device technology. Such circuits, where a supply voltage of V[0002] dd is present, generate a maximum achievable voltage of 2Vdd−Vtn where Vtn is the threshold voltage of an N-channel field effect transistor (FET). DESCRIPTION OF THE PRIOR ART
    [0003] FIG. 1 illustrates a voltage boosting circuit according to the prior art and FIG. 2 illustrates clock signal waveforms used to drive the circuit. [0003]
    [0004] A pair of N-channel transistors [0004] 1 and 2 are cross-coupled to form a bistable flip-flop, the sources of the transistors being connected to voltage rail Vdd. The drain of each transistor, is connected to the gate of the respective other transistor, and form nodes 3 and 4 which are connected through corresponding N-channel transistors 5 and 6 configured as diodes, to one terminal of a capacitor 7. The other terminal of capacitor 7 is connected to ground.
    [0005] A clock source is connected through an inverter [0005] 8 and via capacitor 9 to node 4, and another clock source is connected through an inverter 10 through capacitor 11 to node 3.
    [0006] The clock source voltage at the output of inverter [0006] 8 is shown as waveform φ2, varying between voltages Vdd and Vss, and the clock source output at the output of inverter 10 is shown as waveform φ1, varying between the voltages Vdd and Vss.
    [0007] The output terminal of the circuit supplies the voltage V[0007] pp at the junction of the capacitor 7 and transistors 5 and 6.
    [0008] Operation of the above-described circuit is well known. As the levels of φ[0008] 1 and φ2 vary as shown in FIG. 2, capacitors 9 and 11 alternately charge between Vss and Vdd and discharge to capacitor 7. The maximum achievable voltage at the output terminal is 2Vdd−Vtn, where Vtn is the threshold of operation of either of transistors 5 or 6.
    [0009] It should be noted that the external supply voltage V[0009] dd can vary between limits defined in the device specification, and also as a result of loading, both static and dynamic of other circuits using the same supply. The threshold voltage Vtn is sensitive to variations in semiconductor processing, temperature and chip supply voltage, and this contributes to significant variation in the boosted supply. Finally the boosted Vpp supply itself varies as a function of load current drawn from capacitor 7. Therefore the voltage at the output terminal, which is supposed to provide a stable word line voltage can vary substantially from the ideal. For example, if Vdd is excessively high, this can cause the output voltage to soar to a level which could be damaging to word line access transistor gate insulation, damaging the memory. If Vdd is low, it is possible that insufficient output voltage could be generated to drive the memory cell access transistors, making memory operation unreliable. SUMMARY OF THE PRESENT INVENTION
    [0010] The present invention is a circuit for providing an output voltage which can be used to drive memory word lines which can be as high as 2V[0010] dd; it does not suffer the reduction of Vtn of the prior art circuit. Thus even if Vdd is low, the word line driving voltage even in the worst case would be higher than that of the prior art, increasing the reliability of operation of the memory.
    [0011] The above is achieved by fully switching the transistors in a boosting circuit, rather than employing N-channel source followers as “diodes”. This eliminates reduction of the boosting voltage by V[0011] tn.
    [0012] Another embodiment of the invention is a circuit for detecting the required word line driving voltage and for regulating the voltage boosting pump by enabling the pump to operate if the boosted voltage is low, causing the word line driving voltages to increase, and inhibiting the pump if the voltage reaches the correct word line voltage. This is achieved by utilizing a sample transistor which matches the memory cell access transistor which is to be enabled from the word line. The word line driving voltage is applied to the sample transistor, and when it begins to conduct current indicating that its threshold of operation has been reached, a current mirror provides an output voltage which is used in a feedback loop to inhibit operation of the voltage pump. Since the sample transistor is identical to the memory access transistor, the exactly correct word line driving voltage is maintained. [0012]
    [0013] Thus accurate regulation of the boosted word line voltage is produced, without the danger of damaging voltages. Because once the correct word line driving voltage is reached, the voltage pump is inhibited, there is no additional power required to charge voltage boosting capacitors higher than this point, saving power. Since the voltage that is exactly that required is generated, improved reliability is achieved because double boot-strap voltages on the chip are eliminated. The circuit is thus of high efficiency. [0013]
    [0014] The first and second embodiments are preferred to be used together, achieving the advantages of both. [0014]
    [0015] The same basic design could also be employed as a negative substrate back-bias voltage (V[0015] bb) generator.
    [0016] An embodiment of the invention is a boosted voltage supply comprising a D.C. voltage supply terminal, first and second capacitors, the first capacitor having one terminal connected to ground and its other terminal to an output terminal, switching apparatus for connecting one terminal of the second capacitor alternately between the voltage supply terminal and ground and connecting the other terminal of the second capacitor alternately between the voltage supply terminal and the output terminal, whereby a boosted voltage regulated to the D.C. voltage supply is provided at the output terminal. [0016]
    [0017] Another embodiment of the invention is a dynamic random access (DRAM) word line supply comprising an increasing voltage supply for the word line for connection to the word line from time to time, a memory cell access transistor for connecting a memory cell capacitor to a bit line having a gate connected to the word line, a sample transistor similar to the memory cell access transistor, apparatus for applying the voltage supply to the sample transistor for turning on the sample transistor at a supply voltage related to the characteristics of the sample transistor, and apparatus for inhibiting increase of the voltage supply upon turn-on of the sample transistor, whereby a voltage supply having a voltage level sufficient to turn-on the memory cell access transistor is provided for connection to the word line. [0017] BRIEF INTRODUCTION TO THE DRAWINGS
    [0018] A better understanding of the invention will be obtained by reference to the detailed description below, in conjunction with the following drawings, in which: [0018]
    [0019] FIG. 1 is schematic diagram of a prior art voltage boosting circuit, [0019]
    [0020] FIG. 2 illustrates clock waveforms used to drive the circuit of FIG. 1, [0020]
    [0021] FIG. 3 is a schematic diagram of an embodiment of the present invention, [0021]
    [0022] FIG. 4 illustrates clock signal waveforms used to operate the circuit of FIG. 3, [0022]
    [0023] FIG. 5 is a schematic diagram of a boosted clock generator, and [0023]
    [0024] FIG. 6 is a partly schematic and partly block diagram illustration of another embodiment of the invention. [0024] DETAILED DESCRIPTION OF THE INVENTION
    [0025] With reference to FIG. 3, a capacitor [0025] 15 is connected in a series circuit between ground and through an N-channel field effect transistor FET 16, configured as a diode, with gate and drain connected to a voltage source Vdd. Transistor 16 charges capacitor 15 to Vdd with an N-channel threshold (Vtn) of Vdd upon startup.
    [0026] A first pair of transistors formed of N-channel FET [0026] 17 and P-channel FET 18 are connected with their source-drain circuits in series between the junction of transistor 16 and capacitor 15 and Vdd, the source of transistor 18 being connected with its substrate to the junction of transistor 16 and capacitor 15. That junction forms the output 19 of the circuit, where the voltage Vpp, the word line supply, is provided.
    [0027] A second pair of transistors, one being P-channel FET [0027] 20 and one being N-channel FET 21 have their source-drain circuits connected in series between the voltage supply Vdd and ground. The source of transistor 20 is connected to voltage supply Vdd with its substrate. A second capacitor 22 is connected between the junctions of the two pairs of transistors.
    [0028] While the above-described circuit would operate in a manner to be described below to generate a voltage 2V[0028] dd at the output 19, it provides only a half wave boosting function, and should significant current be drawn, the voltage could drop. In order to provide a full wave boosting function, an additional circuit is included as follows.
    [0029] A third pair of transistors comprising N-channel FET [0029] 23 and P-channel FET 24 have their source-drain circuits connected in series between Vdd and the output terminal 19, the source of transistor 24 being connected to the output terminal with its substrate. A fourth pair of FETs comprised of P-channel FET 24 and N-channel FET 25 have their source-drain circuits connected in series between Vdd and ground, the source of transistor 24 being connected to Vdd with its substrate. A third capacitor 27 is connected between the junctions of the third and fourth pairs of transistors.
    [0030] Clock sources are applied to the gates of the various transistors as follows: φ[0030] 1 to the gate of transistor 25, /φ1 to the gate of transistor 20, φ2 to the gate of transistor 21, and /φ2 to the gate of transistor 26.
    [0031] Boosted clock signals are applied to the gates of the various transistors as follows: φ[0031] 1+ to the gate of transistor 23, /φ1 to the gate of transistor 18, φ2+ to the gate of transistor 17 and /φ2+ to the gate of transistor 24.
    [0032] A schematic of a clock generator is shown in FIG. 5. P-channel transistors [0032] 51 and 52 are cross-coupled to form a bistable flip-flop, the sources and substrates of the transistors being connected to the Vpp output 19, the gate of transistor 52 being connected to the drain of transistor 51 and the gate of transistor 51 being connected to the drain of transistor 52. N-channel transistor 53 has its source-drain circuit connected between the drain of transistor 51 and ground and N-channel transistor 54 has its source-drain circuit connected between the drain of transistor 52 and ground. The clock φ1 is applied to the gate of transistor 54 and the clock /φ1 is applied to the gate of transistor 53.
    [0033] When the clock φ[0033] 1 goes high, transistor 54 is enabled and the junction of transistors 52 and 54 is pulled to ground, enabling transistor 51 which passes Vpp to the junction of transistors 51 and 53. This is the clock φ1+, boosted to Vpp. When the clock φ1 goes low, and /φ1 goes high, transistor 54 is inhibited and transistor 53 is enabled and the junction of transistors 51 and 53 (φ1+) is pulled to ground. This enables transistor 52 which passes Vpp to the junction of transistors 52 and 54, the clock /φ1+ output.
    [0034] A similar circuit (not shown) provides boosted clocks φ[0034] 2+ and /φ2+.
    [0035] FIG. 4 illustrates the clock signal logic levels and timing which are applied to the various gates, and reference is made thereto for the explanation below. [0035]
    [0036] In operation, at initialization, capacitor [0036] 15 is charged through the N-channel FET diode 16 from Vdd, charging it up to Vdd−Vtn. The circuit then goes through a number of cycles to charge up reservoir capacitor 15 to the required level. The following discussion describes the voltages and charge transfers occurring in the pump circuit once the Vpp level has almost reached the desired level, and is sufficient to fully turn on an N-channel transistor with its source at Vdd.
    [0037] Now considering the switching circuit for capacitor [0037] 27 to the left of diode 16, and the waveforms of FIG. 4, φ1 and /φ1+ go high, enabling transistors 23 and 25. Capacitor 27 charges to the level of Vdd. Transistors 23 and 25 are then inhibited, ceasing conduction at the end of the φ1 pulse.
    [0038] After a discrete period of time, /φ[0038] 2 and /φ2+ go low and transistors 24 and 26 are enabled. The capacitor terminal which was connected to Vdd becomes connected to output terminal 19 and the other, negative terminal of capacitor 27 becomes connected to Vdd. If capacitance CR (15) was equal to 0, the voltage from the positive terminal of capacitor 27, at terminal 19 to ground would be equal to the initial voltage on capacitor 27 plus the voltage Vdd to ground, i.e. 2Vdd. However, reservoir capacitor CR (15) typically has a large value so that the voltage step at node 19 will be attenuated to (CS/(CS+CR))*(2Vdd−Vpp), where CR and CS are the values of capacitors 15 and 22 or 27 respectively. Thus the pump can attain a maximum level of 2Vdd.
    [0039] The voltage pulses /φ[0039] 2 and /φ2+ then go high, inhibiting transistors 23 and 25, and after a discrete period of time φ1 and /φ1+ go high again, reconnecting capacitor 27 between Vdd and ground. Again it charges, and as capacitor 27 is alternately switched between Vdd and ground and output terminal 19 and Vdd, the voltage between terminal 19 and ground rises to 2Vdd.
    [0040] A similar function occurs with capacitor [0040] 22. When the clock voltage /φ1 and /φ1+ go low, capacitor 27 is connected between terminal 19 and Vdd through transistors 20 and 18. When the clock voltages φ2 and φ2+ go high, capacitor 22 is connected between Vdd and ground via transistors 17 and 21, charging capacitor 22 to the voltage Vdd. Thus, while capacitor 27 is being charged between Vdd and ground, capacitor 22 is connected between output terminal 19 and Vdd through FETs 20 and 18, due to the phase and polarity of the clock signals /φ1. The two capacitors 27 and 22 thus alternately charge and boost the voltage on capacitor 15.
    [0041] The clock signals φ[0041] 1, φ2, /φ1 and /φ2 have similar amplitudes, and vary between Vdd, a logic 1, and a Vss, a logic zero.
    [0042] The clock signals φ[0042] 1+, φ2+, /φ1+ and /φ2+ have similar amplitudes, and vary between Vpp, a logic 1, and Vss (ground), and logic 0.
    [0043] It should be noted that the capacitors [0043] 15, 22 and 27 charge from the main voltage supply Vdd, and not from the clock sources. This allows the clock sources to have reduced power supply requirements, since they drive only the gates of the FETs which have minimal capacitance. This is in contrast to the prior art boosting circuit in which the clock sources supply the charge required for capacitors 9 and 11 (FIG. 1), and thus supply the current required to boost the voltage, indirectly supplying part of the word line current.
    [0044] In addition, since the voltage boosting current is not routed through an FET configured as a diode, as in the prior art circuit, there is no reduction of the boosting voltage by a threshold of conduction voltage V[0044] tn as in the prior art.
    [0045] Since non-overlapping clocks are used, the boosting current will not flow between the output terminal [0045] 19 and Vdd. This also prevents charge from leaking away from the capacitor 15 during switching.
    [0046] It is preferred that the N-channel transistor substrates should all be connected to a voltage V[0046] ss or Vbb which is below Vss (ground) in this embodiment. The connection of the substrates of the P-channel transistors 24 and 18 to Vpp avoids forward biasing of the P-channel tubs.
    [0047] Turning now to FIG. 6, a word line supply is shown. A word line voltage source such as provided on lead [0047] 29 is connected through a word line decoder 30 to a word line 31. A memory cell access transistor 32 has its gate connected to the word line, and its source-drain circuit connected to a bit line 33 and to a memory cell bit storage capacitor 34. The capacitor is referenced to the cell plate reference voltage Vref.
    [0048] In operation of the above well-known circuit, if a voltage V[0048] pp on lead 29 is supplied through a word line decoder 30 to a word line 31, which voltage is applied to the gate of transistor 32, the bit storage charge capacitor 34 is connected to bit line 33 through transistor 32. The charge stored on capacitor 34 is thereby transferred to bit line 33.
    [0049] The circuit of FIG. 6 provides a word line voltage regulator. A sample transistor [0049] 35 is fabricated identical to word line access transistor 32. It thus exhibits the same characteristics, including the same thresholds of conduction.
    [0050] The source of transistor [0050] 35 is connected to the voltage supply Vdd and the drain is connected through a P-channel transistor 36 to the word line voltage source lead 29. The gate of transistor 36 is connected to its drain.
    [0051] A P-channel transistor [0051] 37 mirrors the current in transistor 36 having its gate connected to the gate and drain of transistor 36, its source connected to the word line voltage source lead 29 and the drain connected to the drain of N-channel transistor 38, which has its other source connected S to ground (Vss), and its gate connected to Vdd, to operate in the linear region as a resistor.
    [0052] Transistors [0052] 36 and 37 form a current mirror of current passing through transistor 36. When Vpp rises to the point at which transistor 35 begins to conduct, a similar current is conducted through transistor 38. A positive voltage appears between the junction of transistors 37 and 38 and ground. This voltage is used as a feedback voltage to inhibit the generation of additional increase in voltage of Vpp on lead 29.
    [0053] Since transistor [0053] 35 is identical to transistor 32, the exactly correct Vpp sufficient to turn on transistor 32 is set.
    [0054] The voltage V[0054] pp at lead 29 can be provided by means of a pump in accordance with the prior art, or preferably the voltage pump 39 described with reference to FIGS. 3 and 4 above. Either the prior art pump or the pump in accordance with the present invention is driven by an oscillator 40, which provides the clock signals, e.g. φ1, φ2, /φ1 and /φ2. Oscillator 44 has an inhibit input, which stops its operation upon receipt of an inhibit signal.
    [0055] The feedback voltage from the current mirror is applied via a pair of serially connected inverters [0055] 41 and 42 to the inhibit input of oscillator 44. Actually, any even number of inverters could be used. Therefore when transistor 35 begins conduction, signifying that the correct word line (and transistor 32) driving voltage Vpp has been reached, the feedback voltage to the inhibit input of oscillator 44 shuts oscillator 44 down, causing cessation of the charging of the capacitors in the voltage boosting circuits, and cessation of increasing of the voltage Vpp.
    [0056] The voltage regulator described above thus eliminates the boosting of V[0056] pp if it is not required, and only allows the voltage boosting circuit to boost the voltage to the level required by the word line, i.e. cell access transistors. This saves power and provides protection to the cell access transistors, increasing reliability of the memory. The dangerous double boot-strap circuits boosting voltage to about 2Vdd which were previously found on the chip are thus eliminated, and voltage stress is minimized.
    [0057] Narrow channel transistors can have higher than expected threshold voltages under back-bias conditions, and the present regulator which actually measures the memory cell access transistor turn-on voltage provides the exact word line supply voltage, neither too low nor too high. The combined embodiments of FIGS. 3 and 5 thus provide a substantially more reliable word line voltage, resulting in a more reliable memory, with reduced power requirements. [0057]
    [0058] A person understanding this invention may now conceive of alternative structures and embodiments or variations of the above. All of those which fall within the scope of the claims appended hereto are considered to be part of the present invention. [0058]
    权利要求:
    Claims (2)
    [1" id="US-20010009518-A1-CLM-00001] 1. A boosted voltage supply comprising:
    DC voltage supply providing plural voltage levels;
    a boosting capacitor having first and second terminals; and
    a switching circuit including a first transistor between one level of the voltage supply and the first terminal of the boosting capacitor and a second transistor between the first terminal of the boosting capacitor and a capacitive load, the first transistor and the second transistor being driven by clock signals, the switching circuit alternately connecting the first terminal of the boosting capacitor to the voltage supply and to the capacitive load while alternating the level of the voltage supply connected to the second terminal of the boosting capacitor to pump the voltage on the capacitive load to a boosted voltage level greater than and of the same polarity as the DC voltage supply, the second transistor being fully switched to substantially eliminate a threshold voltage reduction of boosted voltage.
    [2" id="US-20010009518-A1-CLM-00002] 2. A method of supplying a boosted voltage comprising:
    providing plural voltage levels and a boosting capacitor having first and second terminals; and
    with clock signals applied to switches, alternately switching the first terminal of the boosting capacitor to the voltage supply and to a capacitive load while alternating the level of the voltage supply connected to the second terminal of the boosting capacitor to pump the capacitive load to a boosted voltage level greater than and of the same polarity as the DC voltage supply, the switch between the first terminal of the boosting capacitor and the capacitive load being fully switched to substantially eliminate a threshold voltage reduction of boosted voltage.
    类似技术:
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    公开号 | 公开日
    US20020075706A1|2002-06-20|
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    US6980448B2|2005-12-27|
    US6055201A|2000-04-25|
    GB2244392A|1991-11-27|
    US20070200611A1|2007-08-30|
    US6580654B2|2003-06-17|
    US20040036456A1|2004-02-26|
    US5699313A|1997-12-16|
    US6236581B1|2001-05-22|
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    GB9007791D0|1990-06-06|
    引用文献:
    公开号 | 申请日 | 公开日 | 申请人 | 专利标题
    US20060022928A1|2004-07-29|2006-02-02|Jinoh Kim|Capacitive load charge-discharge device and liquid crystal display device having the same|
    EP1895646A1|2006-09-01|2008-03-05|STMicroelectronicsLimited|Improvements in or relating to charge pumps|US185160A||1876-12-12||Improvement in solutions for galvanic batteries |
    US62066A||1867-02-12||Hieam pulse |
    US2184902A|1939-05-02|1939-12-26|Antony Henry|Hand protector for knives|
    US3387286A|1967-07-14|1968-06-04|Ibm|Field-effect transistor memory|
    GB1348285A|1971-07-26|1974-03-13|Integrated Photomatrix Ltd|Voltage generator|
    US3727196A|1971-11-29|1973-04-10|Mostek Corp|Dynamic random access memory|
    US3801831A|1972-10-13|1974-04-02|Motorola Inc|Voltage level shifting circuit|
    US3942047A|1974-06-03|1976-03-02|Motorola, Inc.|MOS DC Voltage booster circuit|
    GB1504867A|1974-06-05|1978-03-22|Rca Corp|Voltage amplitude multiplying circuits|
    US4001606A|1974-06-05|1977-01-04|Andrew Gordon Francis Dingwall|Electrical circuit|
    GB1502270A|1974-10-30|1978-03-01|Hitachi Ltd|Word line driver circuit in memory circuit|
    JPS6028232B2|1975-08-14|1985-07-03|Sharp Kk||
    US4037114A|1975-10-23|1977-07-19|Rca Corporation|Tri-state logic circuit|
    US4039862A|1976-01-19|1977-08-02|Rca Corporation|Level shift circuit|
    US4047091A|1976-07-21|1977-09-06|National Semiconductor Corporation|Capacitive voltage multiplier|
    US4080539A|1976-11-10|1978-03-21|Rca Corporation|Level shift circuit|
    US4106086A|1976-12-29|1978-08-08|Rca Corporation|Voltage multiplier circuit|
    US4199806A|1978-01-18|1980-04-22|Harris Corporation|CMOS Voltage multiplier|
    DE2821418A1|1978-05-16|1979-11-22|Siemens Ag|CLOCK CONTROLLED DC VOLTAGE CONVERTER|
    US4344005A|1978-07-18|1982-08-10|Rca Corporation|Power gated decoding|
    US4189782A|1978-08-07|1980-02-19|Rca Corporation|Memory organization|
    US4533843A|1978-09-07|1985-08-06|Texas Instruments Incorporated|High performance dynamic sense amplifier with voltage boost for row address lines|
    US4543500A|1978-09-22|1985-09-24|Texas Instruments Incorporated|High performance dynamic sense amplifier voltage boost for row address lines|
    US4216390A|1978-10-04|1980-08-05|Rca Corporation|Level shift circuit|
    US4208595A|1978-10-24|1980-06-17|International Business Machines Corporation|Substrate generator|
    JPS5662066A|1979-10-25|1981-05-27|Nec Corp|Boosting circuit|
    US4338569A|1980-03-11|1982-07-06|Control Data Corporation|Delay lock loop|
    US4307333A|1980-07-29|1981-12-22|Sperry Corporation|Two way regulating circuit|
    US4344003A|1980-08-04|1982-08-10|Rca Corporation|Low power voltage multiplier circuit|
    US4403158A|1981-05-15|1983-09-06|Inmos Corporation|Two-way regulated substrate bias generator|
    JPH0347611B2|1981-06-02|1991-07-19|Tokyo Shibaura Electric Co||
    JPH0143464B2|1981-11-26|1989-09-20|Fujitsu Ltd||
    US4433253A|1981-12-10|1984-02-21|Standard Microsystems Corporation|Three-phase regulated high-voltage charge pump|
    US4486670A|1982-01-19|1984-12-04|Intersil, Inc.|Monolithic CMOS low power digital level shifter|
    US4673829A|1982-02-08|1987-06-16|Seeq Technology, Inc.|Charge pump for providing programming voltage to the word lines in a semiconductor memory array|
    US4511811A|1982-02-08|1985-04-16|Seeq Technology, Inc.|Charge pump for providing programming voltage to the word lines in a semiconductor memory array|
    US4442481A|1982-04-07|1984-04-10|Honeywell Inc.|Low power decoder circuit|
    US4733108A|1982-06-28|1988-03-22|Xerox Corporation|On-chip bias generator|
    US4527258A|1982-09-30|1985-07-02|Mostek Corporation|E2 PROM having bulk storage|
    JPS6146977B2|1983-03-10|1986-10-16|Tokyo Shibaura Electric Co||
    JPS59213090A|1983-05-18|1984-12-01|Toshiba Corp|Driving circuit|
    JPH0531236B2|1983-06-15|1993-05-12|Hitachi Ltd||
    DE3335423A1|1983-09-29|1985-04-04|Siemens AG, 1000 Berlin und 8000 München|VOLTAGE MULTIPLE CIRCUIT|
    US4581546A|1983-11-02|1986-04-08|Inmos Corporation|CMOS substrate bias generator having only P channel transistors in the charge pump|
    JPH077599B2|1984-05-25|1995-01-30|株式会社日立製作所|Semiconductor integrated circuit device|
    US4692638A|1984-07-02|1987-09-08|Texas Instruments Incorporated|CMOS/NMOS decoder and high-level driver circuit|
    US4638182A|1984-07-11|1987-01-20|Texas Instruments Incorporated|High-level CMOS driver circuit|
    JPH0467720B2|1984-08-10|1992-10-29|Fujitsu Ltd||
    US4637018A|1984-08-29|1987-01-13|Burroughs Corporation|Automatic signal delay adjustment method|
    US4639622A|1984-11-19|1987-01-27|International Business Machines Corporation|Boosting word-line clock circuit for semiconductor memory|
    US4656373A|1984-11-26|1987-04-07|Rca Corporation|High-speed voltage level shift circuit|
    JPH0738583B2|1985-01-26|1995-04-26|株式会社東芝|Semiconductor integrated circuit|
    US4583157A|1985-02-08|1986-04-15|At&T Bell Laboratories|Integrated circuit having a variably boosted node|
    JPH0518198B2|1985-04-05|1993-03-11|Fujitsu Ltd||
    US4678941A|1985-04-25|1987-07-07|International Business Machines Corporation|Boost word-line clock and decoder-driver circuits in semiconductor memories|
    US4628214A|1985-05-22|1986-12-09|Sgs Semiconductor Corporation|Back bias generator|
    JPH0470716B2|1985-06-20|1992-11-11|Mitsubishi Electric Corp||
    US4670861A|1985-06-21|1987-06-02|Advanced Micro Devices, Inc.|CMOS N-well bias generator and gating system|
    US4845437A|1985-07-09|1989-07-04|Minolta Camera Kabushiki Kaisha|Synchronous clock frequency conversion circuit|
    EP0209805B1|1985-07-22|1993-04-07|Hitachi, Ltd.|Semiconductor device having bipolar transistor and insulated gate field effect transistor|
    US5086238A|1985-07-22|1992-02-04|Hitachi, Ltd.|Semiconductor supply incorporating internal power supply for compensating for deviation in operating condition and fabrication process conditions|
    US5197033A|1986-07-18|1993-03-23|Hitachi, Ltd.|Semiconductor device incorporating internal power supply for compensating for deviation in operating condition and fabrication process conditions|
    JPH07111825B2|1985-07-22|1995-11-29|株式会社日立製作所|Semiconductor memory device|
    US5051959A|1985-08-14|1991-09-24|Fujitsu Limited|Complementary semiconductor memory device including cell access transistor and word line driving transistor having channels of different conductivity type|
    US4621315A|1985-09-03|1986-11-04|Motorola, Inc.|Recirculating MOS charge pump|
    US4636930A|1985-10-01|1987-01-13|Maxim Integrated Products, Inc.|Integrated dual charge pump power supply and RS-232 transmitter/receiver|
    US4642798A|1985-10-01|1987-02-10|Intel Corporation|CMOS E2 PROM decoding circuit|
    US4679134A|1985-10-01|1987-07-07|Maxim Integrated Products, Inc.|Integrated dual charge pump power supply and RS-232 transmitter/receiver|
    US4689504A|1985-12-20|1987-08-25|Motorola, Inc.|High voltage decoder|
    JP2753218B2|1986-01-31|1998-05-18|株式会社日立製作所|Semiconductor storage device|
    JPS62189816A|1986-02-17|1987-08-19|Hitachi Ltd|Drive circuit|
    JPH0817032B2|1986-03-12|1996-02-21|株式会社日立製作所|Semiconductor integrated circuit device|
    US4795985A|1986-04-01|1989-01-03|Hewlett-Packard Company|Digital phase lock loop|
    US4873673A|1986-12-03|1989-10-10|Hitachi, Ltd.|Driver circuit having a current mirror circuit|
    US4751679A|1986-12-22|1988-06-14|Motorola, Inc.|Gate stress test of a MOS memory|
    DE8714849U1|1986-12-23|1987-12-23|Jenoptik Jena Gmbh, Ddr 6900 Jena, Dd||
    DE3884975T2|1987-01-28|1994-02-10|Nec Corp|Semiconductor memory device with improved column selection scheme.|
    JP2560020B2|1987-02-18|1996-12-04|株式会社日立製作所|Semiconductor memory device|
    JPS63209220A|1987-02-26|1988-08-30|Toshiba Corp|Inverter circuit|
    US4814647A|1987-04-06|1989-03-21|Texas Instruments Incorporated|Fast rise time booting circuit|
    US4906056A|1987-04-14|1990-03-06|Mitsubishi Denki Kabushiki Kaisha|High speed booster circuit|
    KR890005159B1|1987-04-30|1989-12-14|삼성전자 주식회사|The generator of back-bias voltage|
    JPS63292488A|1987-05-25|1988-11-29|Mitsubishi Electric Corp|Decoder circuit for semiconductor memory|
    US5101381A|1987-08-31|1992-03-31|Oki Electric Industry Co., Ltd.|Control circuit for EEPROM|
    JPS6462066A|1987-09-01|1989-03-08|Matsushita Graphic Communic|Picture communication equipment|
    JPH07107798B2|1987-11-18|1995-11-15|三菱電機株式会社|Sense amplifier driving device and sense amplifier driving method in dynamic random access memory|
    US4820941A|1988-02-01|1989-04-11|Texas Instruments Incorporated|Decoder driver circuit for programming high-capacitance lines|
    US5101117A|1988-02-17|1992-03-31|Mips Computer Systems|Variable delay line phase-locked loop circuit synchronization system|
    JP2585348B2|1988-02-22|1997-02-26|株式会社東芝|Nonvolatile semiconductor memory device|
    US4807104A|1988-04-15|1989-02-21|Motorola, Inc.|Voltage multiplying and inverting charge pump|
    US5262999A|1988-06-17|1993-11-16|Hitachi, Ltd.|Large scale integrated circuit for low voltage operation|
    US5297097A|1988-06-17|1994-03-22|Hitachi Ltd.|Large scale integrated circuit for low voltage operation|
    US4888738A|1988-06-29|1989-12-19|Seeq Technology|Current-regulated, voltage-regulated erase circuit for EEPROM memory|
    US4823318A|1988-09-02|1989-04-18|Texas Instruments Incorporated|Driving circuitry for EEPROM memory cell|
    EP0363715B1|1988-10-13|1994-06-01|Siemens Aktiengesellschaft|Integrated-voltage multiplier circuit for a low-voltage power supply|
    JPH0821849B2|1988-10-25|1996-03-04|富士通株式会社|Semiconductor memory device|
    US6212089B1|1996-03-19|2001-04-03|Hitachi, Ltd.|Semiconductor memory device and defect remedying method thereof|
    KR0141495B1|1988-11-01|1998-07-15|미다 가쓰시게|Semiconductor memory device and defect remedying method thereof|
    JPH0713880B2|1988-11-21|1995-02-15|株式会社東芝|Non-volatile semiconductor memory|
    JPH0817033B2|1988-12-08|1996-02-21|三菱電機株式会社|Substrate bias potential generation circuit|
    JP2652694B2|1988-12-28|1997-09-10|三菱電機株式会社|Boost circuit|
    JP2684806B2|1989-02-03|1997-12-03|日本電気株式会社|Integrated circuit|
    JPH02246516A|1989-03-20|1990-10-02|Hitachi Ltd|Semiconductor device|
    JPH02246151A|1989-03-20|1990-10-01|Hitachi Ltd|Resistance means, logic circuit, input circuit, fuse-blowing circuit, drive circuit, power-supply circuit and electrostatic protective circuit; semiconductor storage device containing them, and its layout system and test system|
    JP2928263B2|1989-03-20|1999-08-03|株式会社日立製作所|Semiconductor device|
    JP2868789B2|1989-06-20|1999-03-10|株式会社東芝|Semiconductor drive circuit|
    US5036229A|1989-07-18|1991-07-30|Gazelle Microcircuits, Inc.|Low ripple bias voltage generator|
    JP2911918B2|1989-08-30|1999-06-28|富士通株式会社|Semiconductor storage device|
    JPH0793026B2|1989-09-20|1995-10-09|富士通株式会社|Decoder circuit|
    US5264743A|1989-12-08|1993-11-23|Hitachi, Ltd.|Semiconductor memory operating with low supply voltage|
    US5258660A|1990-01-16|1993-11-02|Cray Research, Inc.|Skew-compensated clock distribution system|
    US5151616A|1990-01-23|1992-09-29|Nec Corporation|Cmos high voltage switch|
    US5134616A|1990-02-13|1992-07-28|International Business Machines Corporation|Dynamic ram with on-chip ecc and optimized bit and word redundancy|
    US5159215A|1990-02-26|1992-10-27|Nec Corporation|Decoder circuit|
    US5023465A|1990-03-26|1991-06-11|Micron Technology, Inc.|High efficiency charge pump circuit|
    US5038325A|1990-03-26|1991-08-06|Micron Technology Inc.|High efficiency charge pump circuit|
    US5059815A|1990-04-05|1991-10-22|Advanced Micro Devices, Inc.|High voltage charge pumps with series capacitors|
    US5267201A|1990-04-06|1993-11-30|Mosaid, Inc.|High voltage boosted word line supply charge pump regulator for DRAM|
    GB9007791D0|1990-04-06|1990-06-06|Foss Richard C|High voltage boosted wordline supply charge pump and regulator for dram|
    GB9007796D0|1990-04-06|1990-06-06|Foss Richard C|Dynamic memory row/column redundancy scheme|
    GB9007790D0|1990-04-06|1990-06-06|Lines Valerie L|Dynamic memory wordline driver scheme|
    US5751643A|1990-04-06|1998-05-12|Mosaid Technologies Incorporated|Dynamic memory word line driver|
    US5214602A|1990-04-06|1993-05-25|Mosaid Inc.|Dynamic memory word line driver scheme|
    IL96808A|1990-04-18|1996-03-31|Rambus Inc|Integrated circuit i/o using a high performance bus interface|
    JP3107556B2|1990-06-01|2000-11-13|株式会社東芝|Dynamic semiconductor memory device|
    US5103113A|1990-06-13|1992-04-07|Texas Instruments Incorporated|Driving circuit for providing a voltage boasted over the power supply voltage source as a driving signal|
    US5208776A|1990-07-31|1993-05-04|Texas Instruments, Incorporated|Pulse generation circuit|
    KR930008876B1|1990-08-17|1993-09-16|현대전자산업 주식회사|High voltage generating circuit of semicondcutor device|
    KR920006991A|1990-09-25|1992-04-28|김광호|High Voltage Generation Circuit of Semiconductor Memory Device|
    TW198135B|1990-11-20|1993-01-11|Oki Electric Ind Co Ltd||
    US5109394A|1990-12-24|1992-04-28|Ncr Corporation|All digital phase locked loop|
    JPH04259983A|1991-02-15|1992-09-16|Hitachi Ltd|Semiconductor storage device|
    US5295164A|1991-12-23|1994-03-15|Apple Computer, Inc.|Apparatus for providing a system clock locked to an external clock over a wide range of frequencies|
    KR0113252Y1|1991-12-24|1998-04-14|문정환|Word line voltage supply circuit|
    JPH05234373A|1992-02-20|1993-09-10|Oki Micro Design Miyazaki:Kk|Semiconductor memory device|
    JP3517237B2|1992-03-06|2004-04-12|ラムバス・インコーポレーテッド|Synchronous bus system and memory device therefor|
    US5317202A|1992-05-28|1994-05-31|Intel Corporation|Delay line loop for 1X on-chip clock generation with zero skew and 50% duty cycle|
    US5262934A|1992-06-23|1993-11-16|Analogic Corporation|Bipolar voltage doubler circuit|
    KR950012019B1|1992-10-02|1995-10-13|삼성전자주식회사|Data output buffer of semiconductor memory device|
    JP3078934B2|1992-12-28|2000-08-21|富士通株式会社|Synchronous random access memory|
    US5337284A|1993-01-11|1994-08-09|United Memories, Inc.|High voltage generator having a self-timed clock circuit and charge pump, and a method therefor|
    DE4420095C1|1994-06-09|1995-10-19|Daimler Benz Ag|Ion conductor for electrochemical storage and method for its production|
    US5796673A|1994-10-06|1998-08-18|Mosaid Technologies Incorporated|Delay locked loop implementation in a synchronous dynamic random access memory|
    JP3601901B2|1996-03-26|2004-12-15|株式会社沖マイクロデザイン|Boost circuit|
    US6075740A|1998-10-27|2000-06-13|Monolithic System Technology, Inc.|Method and apparatus for increasing the time available for refresh for 1-t SRAM compatible devices|
    KR100367690B1|2000-12-04|2003-01-14|실리콘세븐|Asynchronous SRAM using DRAM cell and Operating Method thereof|
    US6483377B2|2001-01-10|2002-11-19|Texas Instruments Incorporated|Low slew rate charge pump|
    US6421295B1|2001-02-14|2002-07-16|Elite Semiconductor Memory Technology Inc.|DRAM circuit and its sub-word line driver|
    US6535424B2|2001-07-25|2003-03-18|Advanced Micro Devices, Inc.|Voltage boost circuit using supply voltage detection to compensate for supply voltage variations in read mode voltage|
    KR100481818B1|2002-07-24|2005-04-11|실리콘세븐|SRAM compatible and Burst Accessible Synchronous Memory Device using DRAM cell and Operating Method thereof|
    JP5662066B2|2010-06-30|2015-01-28|キヤノン電子株式会社|Information processing apparatus, control method therefor, program, and information processing system|GB9007790D0|1990-04-06|1990-06-06|Lines Valerie L|Dynamic memory wordline driver scheme|
    GB9007791D0|1990-04-06|1990-06-06|Foss Richard C|High voltage boosted wordline supply charge pump and regulator for dram|
    US5289025A|1991-10-24|1994-02-22|At&T Bell Laboratories|Integrated circuit having a boosted node|
    WO1994011943A1|1992-11-18|1994-05-26|Oki Electric Industry Co., Ltd.|Power supply voltage booster|
    KR0137317B1|1994-12-29|1998-04-29|김광호|Boost circuit of semiconductor memory device|
    US6048734A|1995-09-15|2000-04-11|The Regents Of The University Of Michigan|Thermal microvalves in a fluid flow method|
    US6831493B2|1998-10-30|2004-12-14|Mosaid Technologies Incorporated|Duty cycle regulator|
    US5748547A|1996-05-24|1998-05-05|Shau; Jeng-Jye|High performance semiconductor memory devices having multiple dimension bit lines|
    US7064376B2|1996-05-24|2006-06-20|Jeng-Jye Shau|High performance embedded semiconductor memory devices with multiple dimension first-level bit-lines|
    US20050036363A1|1996-05-24|2005-02-17|Jeng-Jye Shau|High performance embedded semiconductor memory devices with multiple dimension first-level bit-lines|
    IE970055A1|1997-01-29|1998-07-29|Skelbrook Limited|A charge pump circuit|
    KR100273208B1|1997-04-02|2000-12-15|김영환|High efficiency charge pump circuit for semiconductor memory device|
    US6157566A|1997-08-20|2000-12-05|Micron Technology, Inc.|Reduced leakage DRAM storage unit|
    US5933386A|1997-12-23|1999-08-03|Mitsubishi Semiconductor America, Inc.|Driving memory bitlines using boosted voltage|
    KR100280434B1|1998-01-23|2001-03-02|김영환|High voltage generation circuit|
    JP3248576B2|1998-10-05|2002-01-21|日本電気株式会社|Boost circuit and boost method|
    CA2250538A1|1998-10-30|2000-04-30|Mosaid Technologies Incorporated|Duty cycle regulator|
    US6320797B1|1999-02-24|2001-11-20|Micron Technology, Inc.|Method and circuit for regulating the output voltage from a charge pump circuit, and memory device using same|
    US6160723A|1999-03-01|2000-12-12|Micron Technology, Inc.|Charge pump circuit including level shifters for threshold voltage cancellation and clock signal boosting, and memory device using same|
    US6242970B1|1999-09-04|2001-06-05|Texas Instruments Incorporated|Charge-pump device and method of sequencing charge-pump switches|
    JP3910765B2|1999-09-08|2007-04-25|株式会社東芝|Voltage generation circuit and voltage transfer circuit using the same|
    KR100387266B1|1999-12-28|2003-06-11|주식회사 하이닉스반도체|Voltage control circuit|
    US6313712B1|2000-06-13|2001-11-06|International Business Machines Corporation|Low power crystal oscillator having improved long term and short term stability|
    DK200001482A|2000-10-05|2002-04-06|Forskningsct Risoe|Electrochemical cell and process for making same.|
    EP1221760A3|2001-01-05|2002-11-13|Nokia Corporation|Voltage combiner circuit for electrical loads|
    US6483377B2|2001-01-10|2002-11-19|Texas Instruments Incorporated|Low slew rate charge pump|
    KR100374644B1|2001-01-27|2003-03-03|삼성전자주식회사|Voltage booster circuit capable of controlling boosting voltage|
    US6692700B2|2001-02-14|2004-02-17|Handylab, Inc.|Heat-reduction methods and systems related to microfluidic devices|
    US7010391B2|2001-03-28|2006-03-07|Handylab, Inc.|Methods and systems for control of microfluidic devices|
    US7829025B2|2001-03-28|2010-11-09|Venture Lending & Leasing Iv, Inc.|Systems and methods for thermal actuation of microfluidic devices|
    US8895311B1|2001-03-28|2014-11-25|Handylab, Inc.|Methods and systems for control of general purpose microfluidic devices|
    US7323140B2|2001-03-28|2008-01-29|Handylab, Inc.|Moving microdroplets in a microfluidic device|
    US20030016070A1|2001-07-17|2003-01-23|Wenhua Yang|Bootstrap module for multi-stage circuit|
    US6535424B2|2001-07-25|2003-03-18|Advanced Micro Devices, Inc.|Voltage boost circuit using supply voltage detection to compensate for supply voltage variations in read mode voltage|
    US6852287B2|2001-09-12|2005-02-08|Handylab, Inc.|Microfluidic devices having a reduced number of input and output connections|
    US6639864B2|2001-12-18|2003-10-28|Intel Corporation|Flash device operating from a power-supply-in-packageor from a power supply on chip|
    US6809986B2|2002-08-29|2004-10-26|Micron Technology, Inc.|System and method for negative word line driver circuit|
    US6735145B1|2002-11-04|2004-05-11|International Business Machines Corp.|Method and circuit for optimizing power consumption and performance of driver circuits|
    US6833753B2|2002-11-27|2004-12-21|Texas Instruments Incorporated|Method and system for signal dependent boosting in sampling circuits|
    US6798275B1|2003-04-03|2004-09-28|Advanced Micro Devices, Inc.|Fast, accurate and low power supply voltage booster using A/D converter|
    KR100536603B1|2003-07-10|2005-12-14|삼성전자주식회사|Charge pump circuit having select mode|
    EP1654066B1|2003-07-31|2014-11-12|Handylab, Inc.|Processing particle-containing samples|
    JP2005151777A|2003-11-19|2005-06-09|Sanyo Electric Co Ltd|Charge pumping circuit and amplifier|
    US8445946B2|2003-12-11|2013-05-21|International Business Machines Corporation|Gated diode memory cells|
    US7494066B2|2003-12-19|2009-02-24|Semiconductor Energy Laboratory Co., Ltd.|Semiconductor device|
    US7184284B2|2004-03-30|2007-02-27|Micron Technology, Inc.|Closed-loop high voltage booster|
    US8852862B2|2004-05-03|2014-10-07|Handylab, Inc.|Method for processing polynucleotide-containing samples|
    EP1745153B1|2004-05-03|2015-09-30|Handylab, Inc.|Processing polynucleotide-containing samples|
    US7119604B2|2004-06-17|2006-10-10|Taiwan Semiconductor Manufacturing Company, Ltd.|Back-bias voltage regulator having temperature and process variation compensation and related method of regulating a back-bias voltage|
    KR100541370B1|2004-09-06|2006-01-10|주식회사 하이닉스반도체|Semiconductor memory device|
    EP1645994A1|2004-10-07|2006-04-12|EM Microelectronic-Marin SA|Passive transponder having a voltage booster circuit|
    US8035148B2|2005-05-17|2011-10-11|Analog Devices, Inc.|Micromachined transducer integrated with a charge pump|
    EP1968071B1|2005-12-28|2011-08-24|International Business Machines Corporation|Memory system for reducing current consumption and method thereof|
    US8105783B2|2007-07-13|2012-01-31|Handylab, Inc.|Microfluidic cartridge|
    EP2001990B1|2006-03-24|2016-06-29|Handylab, Inc.|Integrated system for processing microfluidic samples, and method of using same|
    US8088616B2|2006-03-24|2012-01-03|Handylab, Inc.|Heater unit for microfluidic diagnostic system|
    US9186677B2|2007-07-13|2015-11-17|Handylab, Inc.|Integrated apparatus for performing nucleic acid extraction and diagnostic testing on multiple biological samples|
    US7998708B2|2006-03-24|2011-08-16|Handylab, Inc.|Microfluidic system for amplifying and detecting polynucleotides in parallel|
    US8133671B2|2007-07-13|2012-03-13|Handylab, Inc.|Integrated apparatus for performing nucleic acid extraction and diagnostic testing on multiple biological samples|
    WO2008060604A2|2006-11-14|2008-05-22|Handylab, Inc.|Microfluidic system for amplifying and detecting polynucleotides in parallel|
    US10900066B2|2006-03-24|2021-01-26|Handylab, Inc.|Microfluidic system for amplifying and detecting polynucleotides in parallel|
    FR2900752B1|2006-05-05|2008-10-10|Inside Contactless Sa|METHOD AND DEVICE FOR DATA TRANSMISSION BY LOAD MODULATION|
    JP5261888B2|2006-05-18|2013-08-14|富士通セミコンダクター株式会社|Semiconductor memory device|
    KR100798797B1|2006-06-30|2008-01-29|주식회사 하이닉스반도체|Semiconductor memory device with internal voltage generator and therefor operation method|
    US8765076B2|2006-11-14|2014-07-01|Handylab, Inc.|Microfluidic valve and method of making same|
    US7466188B2|2006-12-21|2008-12-16|International Business Machines Corporation|Stress control mechanism for use in high-voltage applications in an integrated circuit|
    KR100870433B1|2007-06-08|2008-11-26|주식회사 하이닉스반도체|Semiconductor device|
    US8287820B2|2007-07-13|2012-10-16|Handylab, Inc.|Automated pipetting apparatus having a combined liquid pump and pipette head system|
    US9618139B2|2007-07-13|2017-04-11|Handylab, Inc.|Integrated heater and magnetic separator|
    USD787087S1|2008-07-14|2017-05-16|Handylab, Inc.|Housing|
    US20090136385A1|2007-07-13|2009-05-28|Handylab, Inc.|Reagent Tube|
    US8182763B2|2007-07-13|2012-05-22|Handylab, Inc.|Rack for sample tubes and reagent holders|
    EP3222733B1|2007-07-13|2021-04-07|Handylab, Inc.|Polynucleotide capture materials, and methods of using same|
    US8044705B2|2007-08-28|2011-10-25|Sandisk Technologies Inc.|Bottom plate regulation of charge pumps|
    US7710195B2|2008-02-15|2010-05-04|International Business Machines Corporation|Two stage voltage boost circuit with precharge circuit preventing leakage, IC and design structure|
    US7737766B2|2008-02-15|2010-06-15|International Business Machines Corporation|Two stage voltage boost circuit, IC and design structure|
    US7733161B2|2008-02-15|2010-06-08|International Business Machines Corporation|Voltage boost system, IC and design structure|
    US7969235B2|2008-06-09|2011-06-28|Sandisk Corporation|Self-adaptive multi-stage charge pump|
    US8710907B2|2008-06-24|2014-04-29|Sandisk Technologies Inc.|Clock generator circuit for a charge pump|
    USD618820S1|2008-07-11|2010-06-29|Handylab, Inc.|Reagent holder|
    USD621060S1|2008-07-14|2010-08-03|Handylab, Inc.|Microfluidic cartridge|
    US9000745B2|2009-04-10|2015-04-07|Taiwan Semiconductor Manufacturing Company, Ltd.|Switching regulator and method for operating the same|
    US8618784B2|2009-04-10|2013-12-31|Taiwan Semiconductor Manufacturing Company, Ltd.|Regulator control circuits, switching regulators, systems, and methods for operating switching regulators|
    US20100308899A1|2009-06-04|2010-12-09|Pericom Semiconductor Corp.|Dual-Output Triple-Vdd Charge Pump|
    US7973592B2|2009-07-21|2011-07-05|Sandisk Corporation|Charge pump with current based regulation|
    US8339183B2|2009-07-24|2012-12-25|Sandisk Technologies Inc.|Charge pump with reduced energy consumption through charge sharing and clock boosting suitable for high voltage word line in flash memories|
    US20110026323A1|2009-07-30|2011-02-03|International Business Machines Corporation|Gated Diode Memory Cells|
    US20110148509A1|2009-12-17|2011-06-23|Feng Pan|Techniques to Reduce Charge Pump Overshoot|
    JP5197704B2|2010-09-22|2013-05-15|株式会社東芝|Semiconductor device|
    US8294509B2|2010-12-20|2012-10-23|Sandisk Technologies Inc.|Charge pump systems with reduction in inefficiencies due to charge sharing between capacitances|
    US8339185B2|2010-12-20|2012-12-25|Sandisk 3D Llc|Charge pump system that dynamically selects number of active stages|
    EP2697657B8|2011-04-15|2017-08-16|Becton, Dickinson and Company|Scanning real-time microfluidic thermocycler and methods for synchronized thermocycling and scanning optical detection|
    US8699247B2|2011-09-09|2014-04-15|Sandisk Technologies Inc.|Charge pump system dynamically reconfigurable for read and program|
    US8400212B1|2011-09-22|2013-03-19|Sandisk Technologies Inc.|High voltage charge pump regulation system with fine step adjustment|
    US8514628B2|2011-09-22|2013-08-20|Sandisk Technologies Inc.|Dynamic switching approach to reduce area and power consumption of high voltage charge pumps|
    EP3273253B1|2011-09-30|2020-08-26|Becton, Dickinson and Company|Unitized reagent strip|
    USD692162S1|2011-09-30|2013-10-22|Becton, Dickinson And Company|Single piece reagent holder|
    CN104204812B|2012-02-03|2018-01-05|贝克顿·迪金森公司|The external file that compatibility determines between distributing and test for molecule diagnostic test|
    WO2013169235A1|2012-05-08|2013-11-14|Intel Corporation|Adaptive voltage input to a charge pump|
    US8912065B2|2012-06-15|2014-12-16|Nanya Technology Corporation|Method of fabricating semiconductor device|
    US8710909B2|2012-09-14|2014-04-29|Sandisk Technologies Inc.|Circuits for prevention of reverse leakage in Vth-cancellation charge pumps|
    US8836412B2|2013-02-11|2014-09-16|Sandisk 3D Llc|Charge pump with a power-controlled clock buffer to reduce power consumption and output voltage ripple|
    US8981835B2|2013-06-18|2015-03-17|Sandisk Technologies Inc.|Efficient voltage doubler|
    US9024680B2|2013-06-24|2015-05-05|Sandisk Technologies Inc.|Efficiency for charge pumps with low supply voltages|
    US9077238B2|2013-06-25|2015-07-07|SanDisk Technologies, Inc.|Capacitive regulation of charge pumps without refresh operation interruption|
    US9007046B2|2013-06-27|2015-04-14|Sandisk Technologies Inc.|Efficient high voltage bias regulation circuit|
    US9083231B2|2013-09-30|2015-07-14|Sandisk Technologies Inc.|Amplitude modulation for pass gate to improve charge pump efficiency|
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    法律状态:
    2004-01-20| CC| Certificate of correction|
    2007-02-02| FPAY| Fee payment|Year of fee payment: 4 |
    2008-07-15| AS| Assignment|Owner name: MOSAID TECHNOLOGIES INCORPORATED, CANADA Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:GILLINGHAM, PETER, MR.;REEL/FRAME:021238/0838 Effective date: 20080618 |
    2009-04-15| AS| Assignment|Owner name: MOSAID TECHNOLOGIES INCORPORATED, CANADA Free format text: CHANGE OF ADDRESS OF ASSIGNEE;ASSIGNOR:MOSAID TECHNOLOGIES INCORPORATED;REEL/FRAME:022542/0876 Effective date: 20090209 Owner name: MOSAID TECHNOLOGIES INCORPORATED,CANADA Free format text: CHANGE OF ADDRESS OF ASSIGNEE;ASSIGNOR:MOSAID TECHNOLOGIES INCORPORATED;REEL/FRAME:022542/0876 Effective date: 20090209 |
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    2015-04-10| REMI| Maintenance fee reminder mailed|
    2015-09-02| LAPS| Lapse for failure to pay maintenance fees|
    2015-09-28| STCH| Information on status: patent discontinuation|Free format text: PATENT EXPIRED DUE TO NONPAYMENT OF MAINTENANCE FEES UNDER 37 CFR 1.362 |
    2015-10-20| FP| Expired due to failure to pay maintenance fee|Effective date: 20150902 |
    优先权:
    申请号 | 申请日 | 专利标题
    GB909007791A|GB9007791D0|1990-04-06|1990-04-06|High voltage boosted wordline supply charge pump and regulator for dram|
    GB9007791.8||1990-04-06||
    GB9007791||1990-04-06||
    GB9107110A|GB2244392A|1990-04-06|1991-04-05|High voltage boosted word line supply charge pump and regulator for dram|
    GB9107110||1991-04-05||
    US07/680,994|US5267201A|1990-04-06|1991-04-05|High voltage boosted word line supply charge pump regulator for DRAM|
    US08/134,621|US5406523A|1990-04-06|1993-10-12|High voltage boosted word line supply charge pump and regulator for DRAM|
    US41840395A| true| 1995-04-07|1995-04-07||
    US08/921,579|US5828620A|1990-04-06|1997-09-02|High voltage boosted word line supply charge pump and regulator for DRAM|
    US09/178,977|US6055201A|1990-04-06|1998-10-26|High voltage boosted word line supply charge pump and regulator for DRAM|
    US09/483,626|US6236581B1|1990-04-06|2000-01-14|High voltage boosted word line supply charge pump and regulator for DRAM|
    US09/819,488|US6614705B2|1990-04-06|2001-03-28|Dynamic random access memory boosted voltage supply|US09/819,488| US6614705B2|1990-04-06|2001-03-28|Dynamic random access memory boosted voltage supply|
    US10/056,837| US6580654B2|1990-04-06|2002-01-24|Boosted voltage supply|
    US10/463,218| US6980448B2|1990-04-06|2003-06-17|DRAM boosted voltage supply|
    US11/113,816| US20060028899A1|1990-04-06|2005-04-25|DRAM boosted voltage supply|
    US11/701,924| US20070200611A1|1990-04-06|2007-02-02|DRAM boosted voltage supply|
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